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LTC1412 12-Bit, 3Msps, Sampling A/D Converter
FEATURES
s s s s s s s s s s
DESCRIPTION
The LTC (R)1412 is a 12-bit, 3Msps, sampling A/D converter. This high performance device includes a high dynamic range sample-and-hold and a precision reference. Operating from 5V supplies it draws only 150mW. The 2.5V input range is optimized for low noise and low distortion. Most high performance op amps also perform best over this range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Outstanding AC performance includes 72dB S/(N + D) and 82dB SFDR at the Nyquist input frequency of 1.5MHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a high speed 12-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and converter status signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. A digital output driver power supply pin allows direct connection to 3V logic.
Sample Rate: 3Msps 72dB S/(N + D) and 82dB SFDR at Nyquist 0.35LSB INL and 0.25LSB DNL (Typ) Power Dissipation: 150mW External or Internal Reference Operation True Differential Inputs Reject Common Mode Noise 40MHz Full Power Bandwidth Sampling 2.5V Bipolar Input Range No Pipeline Delay 28-Pin SSOP Package
APPLICATIONS
s s s s s s
Telecommunications Digital Signal Processing Mulitplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
5V 10F AVDD LTC1412 EFFECTIVE NUMBER OF BITS AIN+ S/H AIN- 4.0625V COMP 10F VREF BUFFER 2k BUSY CS CONVST OGND
1412 TA01
OPTIONAL 3V LOGIC SUPPLY DVDD OVDD
Effective Bits and Signal-to-Noise + Distortion vs Input Frequency
12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
1412 G01
12 12-BIT ADC OUTPUT BUFFERS
* * *
D11 (MSB)
D0 (LSB)
2.5V REFERENCE AGND
TIMING AND LOGIC DGND
VSS 10F - 5V
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74 68 62 56
S/(N + D) (dB)
1
LTC1412
ABSOLUTE MAXIMUM RATINGS
AVDD = DVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW AIN+ AIN- VREF REFCOMP AGND D11 (MSB) D10 D9 D8 1 2 3 4 5 6 7 8 9 28 AVDD 27 DVDD 26 VSS 25 BUSY 24 CS 23 CONVST 22 DGND 21 DVDD 20 OVDD 19 OGND 18 D0 17 D1 16 D2 15 D3
Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS)................................. - 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS - 0.3V) to 10V Digital Output Voltage ........ (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1412C................................................ 0C to 70C LTC1412I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1412CG LTC1412IG
D7 10 D6 11 D5 12 D4 13 DGND 14
G PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 95C/ W
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) (Note 7)
With internal reference (Notes 5, 6)
MIN
q q q q
CONDITIONS
TYP 0.35 0.25 2
MAX 1 1 6 8 15
UNITS Bits LSB LSB LSB LSB LSB ppm/C
12
IOUT(REF) = 0
q
15
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN tACQ tAP tjitter CMRR
(Note 5)
CONDITIONS 4.75V VDD 5.25V, - 5.25V VSS - 4.75V CS = High Between Conversions During Conversions
q q q
MIN
TYP 2.5
MAX 1
UNITS V A pF pF
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
10 4 20 - 0.5 1 50
psRMS dB
- 2.5V < (AIN = AIN) < 2.5V
-
63
2
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ns ns
LTC1412
DY A IC ACCURACY
SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD SFDR IMD Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS - 4.75V 0.1mA IOUT 0.1mA IOUT = 0
DIGITAL I PUTS AND OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D11 to D0 Hi-Z Output Capacitance D11 to D0 Output Source Current VDD = 5.25V
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD ISS PD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
UW
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(Note 5)
CONDITIONS 100kHz Input Signal 1.465MHz Input Signal 100kHz Input Signal, First 5 Harmonics 1.465MHz Input Signal, First 5 Harmonics 1.465MHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz S/(N + D) 68dB MIN 70 TYP 72.5 72 - 90 - 80 82 - 84 40 4 MAX UNITS dB dB dB dB dB dB MHz MHz
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(Note 5)
MIN 2.480 TYP 2.500 15 0.01 0.01 2 4.06 MAX 2.520 UNITS V ppm/C LSB/ V LSB/ V k V
(Note 5)
MIN
q q q
CONDITIONS VDD = 4.75V VIN = 0V to VDD VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
1.4
q q q
4.0
4.75 4.71 0.05 0.10 7 - 10 0.4 10
V V A pF mA
(Note 5)
CONDITIONS (Note 10) (Note 10) CS High CS High
q q q
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA mW
12 18 150
16 28 220
3
LTC1412
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tCONV tACQ t1 t2 t3 t4 t5 t6 t7 PARAMETER Maximum Sampling Frequency
t8 t9
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD.
TI I G DIAGRA
CS
CONVST t3 BUSY t6 DATA DATA (N - 1) DB11 TO DB0 t4 DATA N DB11 TO DB0 t7 DATA (N + 1) DB11 TO DB0 t5
4
W
UW
UW
(Note 5)
CONDITIONS
q q q q
MIN 3
TYP
MAX 333
UNITS MHz ns ns ns ns ns
Throughput Time (Acquisition + Conversion) Conversion Time Acquisition Time CS to CONVST Setup Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY (Notes 9, 10) (Note 10) CL = 25pF
240 20 5 20 5
283 50
q q q q
20 - 20 - 25 50 10 35 45 30 35 40 0 20 25
ns ns ns ns ns ns ns ns ns ns ns ns
Delay Between Conversions Data Access Time After CS Bus Relinquish Time
(Note 10) CL = 25pF
q q
8 LTC1412C LTC1412I
q q q
CONVST High Time Aperture Delay of Sample-and-Hold
20 -1
Note 5: VDD = 5V, fSAMPLE = 3MHz and tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN input with AIN- grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions.
t1
tCONV t2
1412 TD
LTC1412 TYPICAL PERFOR A CE CHARACTERISTICS
S/(N + D) and Effective Number of Bits vs Input Frequency
12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
1412 G01
SIGNAL-TO-NOISE RATIO (dB)
EFFECTIVE NUMBER OF BITS
DISTORTION (dB)
Spurious-Free Dynamic Range vs Input Frequency
0 0 -20 AMPLITUDE (dB) - 40 - 60 - 80
SPURIOUS-FREE DYNAMIC RANGE (dB)
-10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 -100 10K -120 100K 1M FREQUENCY (Hz) 10M
1412 G04
AMPLITUDE (dB)
Intermodulation Distortion Plot
0 -10 -20 - 30 AMPLITUDE (dB)
DNL (LSBs)
fSMPL = 3MHz fIN1 = 85.693359kHz fIN2 = 114.990234kHz
- 50 - 60 - 70 - 80 - 90
0
INL (LSBs)
- 40
-100 -110
0
200
400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 G05
UW
Signal-to-Noise Ratio vs Input Frequency
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S/(N + D) (dB)
Distortion vs Input Frequency
0 - 20 - 40 - 60 - 80 THD -100 -120 3RD 2ND
80 70 60 50 40 30 20 10 0 10k
100k 1M INPUT FREQUENCY (Hz)
10M
1412 G02
10
100 1k INPUT FREQUENCY (Hz)
10k
1412 G03
Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz
0 fSMPL = 3Msps fIN = 97.412kHz SFDR = 93.3dB SINAD = 73dB -20 - 40 - 60 - 80
Nonaveraged, 4096 Point FFT, Input Frequency = 1.45kHz
fSMPL = 3Msps fIN = 1.419kHz SFDR = 83dB SINAD = 72.5dB SNR = 73db
-100
-100 -120 0 200 400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 F02a
0
200
400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 F02B
Differential Nonlinearity vs Output Code
1.0
1.0
Integral Nonlinearity vs Output Code
0.5
0.5
0
- 0.5
- 0.5
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1412 G06
-1.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1412 G07
5
LTC1412 TYPICAL PERFOR A CE CHARACTERISTICS
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough vs Ripple Frequency
0 COMMON MODE REJECTION (dB) 10M
1412 G08
- 20 - 40 - 60 VSS - 80 -100 -120 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) VDD DGND
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. 2.5V input range when AIN- is grounded. 2.5V differential if AIN- is driven. AIN- (Pin 2): Negative Analog Input. Can be grounded or driven differentially with AIN+. VREF (Pin 3): 2.5V Reference Output. REFCOMP (Pin 4): 4.06V Reference Bypass Pin. Bypass to AGND with 10F ceramic (or 10F tantalum in parallel with 0.1F ceramic). AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground for the Output Drivers. OVDD (Pin 20): Positive Supply for the Output Drivers. Tie to Pin 28 when driving 5V logic. Tie to 3V when driving 3V logic. DVDD (Pin 21): 5V Positive Supply. Tie to Pin 28. Bypass to AGND with 0.1F ceramic. DGND (Pin 22): Digital Ground for Internal Logic. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): Chip Select. This input must be low for the ADC to recognize the CONVST inputs. BUSY (Pin 25): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. VSS (Pin 26): - 5V Negative Supply. Bypass to AGND with 10F ceramic (or 10F tantalum in parallel with 0.1F ceramic). DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10F ceramic (or 10F tantalum in parallel with 0.1F ceramic).
6
UW
Input Common Mode Rejection vs Input Frequency
80 70 60 50 40 30 20 10 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
1412 G09
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LTC1412
FUNCTIONAL BLOCK DIAGRA
AIN+
AIN- 2k VREF 2.5V REF ZEROING SWITCHES
REF AMP
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DBN 1k CL DBN CL
A) HI-Z TO VOH AND VOL TO VOH
B) HI-Z TO VOL AND VOH TO VOL
1412 TC01
APPLICATIONS INFORMATION
Conversion Details The LTC1412 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN- inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 50ns will provide enough time for the
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CSAMPLE CSAMPLE AVDD DVDD
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+
12-BIT CAPACITIVE DAC COMP
-
12
SUCCESSIVE APPROXIMATION REGISTER
OUTPUT LATCHES
* * *
D11 D0 OVDD
CONTROL LOGIC
OGND
1412 BD
CONVST
CS
BUSY
Load Circuits for Output Float Delay
5V 1k DBN 1k 100pF DBN 100pF
A) VOH TO HI-Z
B) VOL TO HI-Z
1412 TC02
7
LTC1412
APPLICATIONS INFORMATION
AIN+ SAMPLE HOLD AIN- SAMPLE HOLD CDAC+ CSAMPLE- CSAMPLE+
0 -20 fSMPL = 3Msps fIN = 97.412kHz SFDR = 93.3dB SINAD = 73dB
ZEROING SWITCHES HOLD
AMPLITUDE (dB)
HOLD
+
VDAC+ CDAC- COMP
-
12 SAR
VDAC-
OUTPUT LATCHES
1412 F01
Figure 1. Simplified Block Diagram
sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN- input charges. The SAR contents (a 12-bit data word) which represents the difference of AIN+ and AIN- are loaded into the 12-bit output latches. Dynamic Performance The LTC1412 has excellent high speed sampling capability. FFT (Fast Four Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1412 FFT plot. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited
AMPLITUDE (dB)
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- 40 - 60 - 80
-100 -120
0
200 400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 F02a
* D11 * * D0
Figure 2a. LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz
0 -20 - 40 - 60 - 80 fSMPL = 3Msps fIN = 1.419kHz SFDR = 83dB SINAD = 72.5dB SNR = 73db
-100 -120
0
200
400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 F02B
Figure 2b. LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency = 1.45MHz
to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 3MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 1.5MHz. Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) - 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 3MHz the LTC1412 maintains near ideal ENOBs up to the Nyquist input frequency of 1.5MHz. Refer to Figure 3.
LTC1412
APPLICATIONS INFORMATION
12 10 8 6 4 2 0 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
1412 G01
74 68 62 56
EFFECTIVE NUMBER OF BITS
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency
Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20 log
2 2 2 2 V2 + V3 + V4 + . . .Vn
AMPLITUDE (dB)
V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through Nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1412 has good distortion performance up to the Nyquist frequency and beyond.
0 - 20
DISTORTION (dB)
- 40 - 60 - 80 THD 3RD 2ND
-100 -120 10
100 1k INPUT FREQUENCY (Hz)
10k
1412 G03
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can
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produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula:
S/(N + D) (dB)
IMD fa + fb = 20 log
0 -10 -20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 -100 -110 0 200
(
)
Amplitude at fa fb Amplitude at f a
fSMPL = 3MHz fIN1 = 85.693359kHz fIN2 = 114.990234kHz
(
)
400 600 800 1000 1200 1400 FREQUENCY (kHz)
1412 G05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1412 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with fre-
9
LTC1412
APPLICATIONS INFORMATION
quencies above the converter's Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1412 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The AIN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1412 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 50ns for full throughput rate).
10
ACQUISITION TIME (s)
1
0.1
0.01 10 100 1k 10k SOURCE RESISTANCE () 100k
1412 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth
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frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1412 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1412. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT(R)1223: 100MHz Video Current Feedback Amplifier. 6mA supply current. 5V to 15V supplies. Low Noise. Good for AC applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. 5V to 15V supplies. Low Noise. Best for AC applications. LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. 2V to 15V supplies. Low Noise. Good AC specifications, 6mA supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. 5V to 15V supplies. Good AC and DC specifications. 70ns settling to 0.5LSB. LT1363: 70MHz, 1000V/s Op Amps. 6.3mA supply current. Good AC and DC specifications. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and Quad 70MHz, 1000V/s Op Amps. 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1412 noise and distortion. The small-signal bandLinearView is a trademark of Linear Technology Corporation.
LTC1412
APPLICATIONS INFORMATION
width of the sample-and-hold circuit is 40MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 7 shows a 500pF capacitor from AIN+ to ground and a 100 source resistor to limit the input bandwidth to 3.2MHz. The 500pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch-sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole
100 ANALOG INPUT 500pF 2 AIN- LTC1412 3 VREF
1
AIN+
4 10F 5
REFCOMP
AGND
1412 F07a
Figure 7a. RC Input Filter
1 8 1 AIN+ AIN- LTC1412 6 3 VREF
VIN
2 LTC1560-1 3
7
2
- 5V
4 0.1F
5
5V 0.1F 10F
4
REFCOMP
5 AGND R3 64k LTC1412
1412 F07b
1412 F08a
5
AGND
Figure 7b. 1MHz Fifth-Order Elliptic Lowpass Filter
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filter is required. Figure 7b shows a simple implementation using an LTC1560-1 fifth-order elliptic continuous time filter. Input Range The 2.5V input range of the LTC1412 is optimized for low noise and low distortion. Most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1412 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1412 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3), see Figure 8a. A 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry, see Figure 8b. The reference amplifier gains the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin, REFCOMP (Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 10F ceramic or 10F tantalum in parallel with a 0.1F ceramic is recommended.
3 VREF R1 2k BANDGAP REFERENCE
2.500V
4.0625V
4 REFCOMP
REFERENCE AMP R2 40k
10F
Figure 8a. LTC1412 Reference Circuit
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LTC1412
APPLICATIONS INFORMATION
1 ANALOG INPUT 5V VIN VOUT LT1019A-2.5 2 AIN- LTC1412 3 VREF AIN+
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0 - 20 - 40 - 60 VSS - 80 -100 -120 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) 10M
1412 G08
4 10F 5
REFCOMP
AGND
1412 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1412 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment.
1 ANALOG INPUT 1.25V TO 3V DIFFERENTIAL AIN+ AIN- LTC1412 LTC1450 1.25V TO 3V 3 VREF
2
4 10F 5
REFCOMP
AGND
Figure 9. Driving VREF with a DAC
Differential Inputs The LTC1412 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ - (AIN- ) independent of the common mode voltage. The common mode rejection holds up to extremely high frequencies, see Figure 10. The only requirement is that both inputs cannot exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common
OUTPUT CODE
12
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VDD DGND
Figure 10. CMRR vs Input Frequency
mode voltage. THD will degrade as the inputs approach either power supply rail, from - 86dB with a common mode of 0V to -75dB with a common mode of 2.5V or - 2.5V. Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1412. The code transitions occur midway between successive integer LSB values (i.e., - FS/2 + 0.5LSB, - FS/2 + 1.5LSB, - FS/2 + 2.5LSB,...FS/2 - 1.5LSB, FS/2 - 0.5LSB). The output is two's complement binary with 1LSB = FS - (- FS)/4096 = 5V/4096 = 1.22mV.
111...111 111...110 111...101
1412 F09
000...010 000...001 000...000 FS - 1LSB INPUT VOLTAGE (V)
1412 F11a
FS - 1LSB
Figure 11a. LTC1412 Transfer Characteristics
In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error apply
LTC1412
APPLICATIONS INFORMATION
- 5V R1 50k R3 24k ANALOG INPUT R4 100 R5 R2 47k 50k R6 24k 10F 5 AGND
1412 F11b
1
AIN+ AIN- LTC1412
2
3
VREF
4
REFCOMP
Figure 11b. Offset and Full-Scale Adjust Circuit
- 0.61mV (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.49817V (FS/2 - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. Board Layout and Bypassing To obtain the best performance from the LTC1412, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital line alongside an analog signal line. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND), Pins 22 and 14 (DGND) and Pin 19 (OGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane, see Figure 12. All analog circuitry grounds should be terminated to this analog ground plane. The ground return from the ground
1
AIN+ AIN- REFCOMP 4 10F 0.1F AGND 5 2
ANALOG INPUT CIRCUITRY
+ -
+
+
10F
ANALOG GROUND PLANE
1412 F12
Figure 12. Power Supply Grounding Practice
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plane to the power supply should be low impedance. Digital circuitry grounds must be connected to the digital supply common. Low impedance analog and digital power supply lines are essential to low noise operation of the ADC. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1412 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN - leads will be rejected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1412 will hold and convert the difference voltage between AIN+ and AIN- . The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN- traces should be run side by side to equalize coupling. Supply Bypassing High quality, low series resistance ceramic, 10F bypass capacitors should be used at the VDD and REFCOMP pins. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Example Layout Figures 13a, 13b, 13c and 13d show the schematic and layout of an evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board.
LTC1412 VSS 26 0.1F AVDD OVDD DVDD DGND 14, 22 OGND 19
DIGITAL SYSTEM 28 10F 20 0.1F 21, 27
+
POWER SUPPLY GROUND
13
LTC1412
D4 D5 6 1 20 1 B[00:11] B0 B1 B2 B3 6 7 8 9 10 B7 11 B6 12 B5 13 B4 15 B3 16 B2 17 B1 18 B0 22 21 B6 C8 0.1F OVDD B5 B4 B7 B8 B9 B10 2 3 4 5 6 7 8 9 11 1 0E CLK D0 D1 D2 D3 D4 D5 D6 Q0 Q1 Q2 Q3 Q4 Q5 Q6 20 OVDD U7 74HC574 19 18 17 16 15 14 13 12 Q7 D7 GND 10 D10 D9 D8 D7 D6 D5 D4 11 B8 9 12 Q7 D7 GND 10 B9 8 D6 Q6 13 B10 7 D5 Q5 14 D1 D3 D5 D7 D9 D11 JP2 HEADER D10 D8 D6 D4 D2 D0 D11 D11 U5E 74HC14 10 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 B11 B11 D4 Q4 6 15 D11 D3 Q3 5 16 D3 D2 Q2 U1 LTC1412 1 2 3 4 5 14 23 24 25 20 C7 0.1F 19 26 27 28 VSS VCC AVDD OVDD DVDD OGND VSS D0 DGND D1 DVDD D2 BUSY D3 CS D4 CONVST D5 DGND D6 AGND D7 REFCOMP D8 VREF D9 -AIN D10 +AIN D11 (MSB) 4 17 D2 D11 D1 Q1 3 18 D1 D0 Q0 2 19 D0 CLK D9 D10 11 0E D8 U6 74HC574 D7 OVDD R8, 1.2k R9, 1.2k D6 R7, 1.2k R6, 1.2k
R5, 1.2k D5 D6 D7 D8 D9 R10, 1.2k D10 R11, 1.2k D11 R12, 1.2k D12 JP1
1 JP5 2 2- VSS 4 8
J1
A+ C9 0.1F
1 JP6 2
R15 51
2
C6 470pF
R18 10k
JP7
1
APPLICATIONS INFORMATION
J2
C10 1F 16V
C11 10F 16V
+
J3 3
CLK
1
U5A 74HC14 2
U5B 74HC14 4
R19 51 1 JP8 2
U4 LT1175 6 5 VSS C13 0.1F C14 0.1F
E1 -7V TO -15V D14 SS12 5 OVDD C19 0.1F U5 DECOUPLING 13 C12 22F 10V U5F 74HC14 12 U5C 74HC14 6
1
SHDN
GND
INPUT
SENSE
4
8
INPUT
OUT
3
2
7
NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES 1/8W, 5% SMT 2. ALL CAPACITOR VALUES 50V, 20% SMT
Figure 13a. LTC1412 Demonstration Board Features Analog Input Signal Buffer, 3Msps, Parallel Data Output 12-Bit ADC, Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 16-Pin Header, P2
+
LIM2
LIM4
9 R13 1k C20 15pF
U5D 74HC14 8
RDY
1412 F13a
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A-
R16 51
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R17 10k
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E2 GND
U3 LT1363 3 75 +
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VCC D0 D1 R2, 1.2k D2 R3, 1.2k D3 R4, 1.2k D4 C3 0.1F D2 D3 C4 0.1F R1, 1.2k VCC 3.3V 2 JP3 1 R14 20 2 JP4 1 OVDD D1 D[0:11]
3.3V
E4 OPTIONAL
U2 LT1121-5
1
E3 7V TO 15V
VIN
VOUT
3
+
C5 10F 10V
TAB 4
GND 2
D13 SS12 VCC C2 0.1F
+
C1 22F 10V
LTC1412
APPLICATIONS INFORMATION
Figure 13b. Component Side Silkscreen
Figure 13c. Component Side
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Figure 13d. Solder Side
15
LTC1412
PACKAGE DESCRIPTION
0.205 - 0.212** (5.20 - 5.38)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER 16-Bit LTC1604 LTC1605 14-Bit LTC1419 LTC1416 LTC1418 12-Bit LTC1410 LTC1415 LTC1409 LTC1279 LTC1404 LTC1278-5 LTC1278-4 LTC1400 12 12 12 12 12 12 12 12 1.25Msps 1.25Msps 800ksps 600ksps 600ksps 500ksps 400ksps 400ksps 150mW, 71.5dB SINAD and 84dB THD 55mW, Single 5V Supply 80mW, 71.5dB SINAD and 84dB THD 60mW, Single 5V or 5V Supply High Speed Serial I/O in SO-8 Package 75mW, Single 5V or 5V Supply 75mW, Single 5V or 5V Supply High Speed Serial I/O in SO-8 Package
1412f LT/TP 0798 4K * PRINTED IN USA
RESOLUTION 16 16 14 14 14
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 - 0.407* (10.07 - 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.0256 (0.65) BSC
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G28 SSOP 0694
SPEED 333ksps 100ksps 800ksps 400ksps 200ksps
COMMENTS 2.5V Input Range, 5V Supply 10V Input Range, Single 5V Supply 150mW, 81.5dB SINAD and 95dB SFDR 75mW, Low Power with Excellent AC Specs 15mW, Single 5V, Serial/Parallel I/O
(c) LINEAR TECHNOLOGY CORPORATION 1998

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